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X28C512, X28C513
Resetting Software Data Protection
V CC
Data
Addr
AAA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥ t WC
Standard
Operating
Mode
CE
WE
Note: All other timings and control pins are per page write timing requirements
FIGURE 5A. Reset Software Data Protection Timing Sequence
System Considerations
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data A0
to Address
5555
Because the X28C512, X28C513 are frequently used in
large memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation and
eliminate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read operation
this assures that all deselected devices are in their standby
mode and that only the selected device(s) is/are outputting
data on the bus.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
FIGURE 5B. SOFTWARE SEQUENCE TO DEACTIVATE
SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After t WC , the X28C512,
X28C513 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
9
Because the X28C512, X28C513 have two power modes,
(standby and active), proper decoupling of the memory array
is of prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on the
output capacitive loading of the I/Os. Therefore, the larger
the array sharing a common bus, the larger the transient
spikes. The voltage peaks associated with the current
transients can be suppressed by the proper selection and
placement of decoupling capacitors. As a minimum, it is
recommended that a 0.1μF high frequency ceramic
capacitor be used between V CC and V SS at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
In addition, it is recommended that a 4.7μF electrolytic bulk
capacitor be placed between V CC and V SS for each 8
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
FN8106.2
June 7, 2006
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